Compute Express Link
The CXL consortium has had a regular presence at FMS (which rechristened itself from 'Flash Memory Summit' to the 'Future of Memory and Storage' this year). Back at FMS 2022, the company had announced v3.0 of the CXL specifications. This was followed by CXL 3.1's introduction at Supercomputing 2023. Having started off as a host to device interconnect standard, it had slowly subsumed other competing standards such as OpenCAPI and Gen-Z. As a result, the specifications started to encompass a wide variety of use-cases by building a protocol on top of the the ubiquitous PCIe expansion bus. The CXL consortium comprises of heavyweights such as AMD and Intel, as well as a large number of startup companies attempting to play in different segments on...
Using a PCIe Slot to Install DRAM: New Samsung CXL.mem Expansion Module
In the computing industry, we’ve lived with PCIe as a standard for a long time. It is used to add any additional features to a system: graphics, storage, USB...
47 by Dr. Ian Cutress on 5/11/2021
CXL Consortium Formally Incorporated, Gets New Board Members & CXL 1.1 Specification
Over four years ago, Intel started to develop what is now known as Compute Express Link (CXL), an interface to coherently connect CPUs to all types of other compute...
5 by Anton Shilov on 9/20/2019
Compute Express Link (CXL): From Nine Members to Thirty Three
Last month the CXL Specification 1.0 was released as a future cache coherent interconnect that uses the PCIe 5.0 physical infrastructure but aimed to provide a breakthrough in utility...
18 by Dr. Ian Cutress on 4/15/2019
CXL Specification 1.0 Released: New Industry High-Speed Interconnect From Intel
With the battleground moving from single core performance to multi-core acceleration, a new war is being fought with how data is moved around between different compute resources. The Interconnect...
48 by Ian Cutress on 3/11/2019
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