Intel Reveals Name of Next Generation Xeon D: Hewitt Lake
by Ian Cutress on February 25, 2019 12:01 AM EST- Posted in
- CPUs
- Intel
- Trade Shows
- Enterprise CPUs
- Xeon-D
- MWC 2019
-page-006_678x452.jpg)
The Xeon D processor line for Intel has been a combination networking/microserver processor that increased significantly in core count, power, and capability in the previous generation. We now have two splits – the 500 family for networking, and 100 family for higher performance. Today Intel is revealing the name of the successor to the D-1500 family: Hewitt Lake.
The D-1500 processors were built upon Skylake-SP silicon designs with on-package chipsets to help accelerate networking functionality as well as implementations of Intel’s Quick Assist Technology (QAT) to process encrypted data streams much faster with appropriate offloading hardware.
Intel doesn’t disclose much about the new processor line. At this point we suspect that they will use the newest Cascade Lake silicon design, which affords additional hardware security against specific Spectre and Meltdown attacks, VNNI instruction extensions, and Optane DC memory support. The big part of these chips will be in the chipset, and there is no obvious indication that Intel is doing something new there at this point.
Intel does state that the new Hewitt Lake processors will have an increase in frequency over the current generation D-1500 NS processors, and are ‘optimized for performance to advance customers down the path of 5G’, but fails to explain exactly what that means.
If previous reports are anything to go by, then Intel will be launching Cascade Lake in the next few months. Cascade Lake derived processors, should Hewitt Lake be related in anyway, are likely to come one or two quarters later.
Related Reading
- Intel Announces Xeon D-1500 Network Series SoCs with QuickAssist, Four 10 GbE Ports
- Living On The Edge: Intel Launches Xeon D-2100 Series SoCs
- Intel to Update Xeon D in Early 2018, with Skylake-SP Cores
Facebook
Twitter
RSS
10 Comments
View All Comments
satai - Monday, February 25, 2019 - link
Freudian misreading: Hewitt "Late".Sorry Intel but it matches your release style.
Achaios - Monday, February 25, 2019 - link
Another 14nm++++++++++++++++++++++++++ chip? *Yawn*shabby - Monday, February 25, 2019 - link
What's yawn about it? It'll run 100mhz higher than the previous 14nm+++++++...Xyler94 - Wednesday, February 27, 2019 - link
If there's no architecture improvements, 100mhz quicker is nothing to be proud of. Just means that yields got better and that Intel can validate the slightly higher speeds. Or maybe, yields haven't improved and Intel is just slightly overclocking the chips.And I haven't seen official specs, but if the 100mhz quicker is in the boost, and not base, then it's even more laughable. Intel only usually gives single core max boost, not all core boost.
Without proper improvements, it's not impressive at all. This seems more to appease investors more than actually releasing a new product. It's like being excited that Chev managed to get 10 HP out of their newest Camero, but nothing about it changed, except the exhaust system. No body changes, no Fuel efficiency changes, no engine changes, just a new exhaust system that managed to add 10HP. (( And yes, exhaust systems can add performance if done right )). It's nothing exciting or innovative, achieving an extra 100mhz.
bcronce - Monday, February 25, 2019 - link
https://www.zdnet.com/article/mwc-2019-intel-annou...This article mentions that there is an FGPA meant to help handle "5G" processing because the 5G spec is not set in stone.
ksec - Tuesday, February 26, 2019 - link
That is the add on card, not something to do with the Xeon-D. It would be nice if they could merge the two down the road.Kevin G - Monday, February 25, 2019 - link
Disappointing. The last Xeon D line up was supposed to be 10 nm as Intel's first server product on that node. Recycling SkyLake-SP ate away much of the efficiency the original Xeon D had but without 10 nm mass production still, Intel didn't have much choice to bring a design to market quickly.The original Xeon D was a play to provide direct competition to the early ARM efforts in the data center from gaining a foothold. Luckily for Intel, the original Xeon D was a great product and the first wave of datacenter ARM chips sort of fizzled with some not reaching the market, significant delays or under performed.
The second wave of ARM chips are coming and Intel again need to revamp the Xeon D line. There is also the wild card of AMD and their chiplet strategy as it provides a means of them providing specialized IO for network acceleration or other accelerators for specific workloads.
mode_13h - Monday, February 25, 2019 - link
This.I never understood what happened with Xeon D gen 2. Was it a conscious shift in strategic direction, or just Intel flailing? Either way, it didn't seem in line with the story around their gen 1 and I'm not sure I really understand what market niche they were going after.
Kevin G - Wednesday, February 27, 2019 - link
Intel's manufacturing side dropped the ball. They went from having a 12 month lead to being ~12 months behind. That equates to some products being two years behind schedule and Intel's competition wasn't going to stand still.Xeon D I think was supposed to be Intel's second major 10 nm part after Cannon Lake. Rumors were pointing to similar core designs but with significantly different IO for each market. (The big 10 nm Xeon SP chips with their dual AVX-512 units and tile interconnect were going to continue to be different than Xeon D).
The Xeon D we got of course were repackaged Xeon SP.
ksec - Tuesday, February 26, 2019 - link
They just need to ramp a Xeon-D line that has additional hardware security against specific Spectre and Meltdown attacks. For the target customer of Xeon-D, those hardware fix will be priority over Speed, and Power / Pref.